1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to a write scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices.
2. Description of the Related Art
There is a demand for faster, higher capacity, random access memory (RAM) devices. RAM devices, such as dynamic random access memory (DRAM) are typically used as the main memory in computer systems. Although the operating speed of the DRAM has improved over the years, the speed has not reached that of the processors used to access the DRAM. In a computer system, for example, the slow access and cycle times of the DRAM lead to system bottlenecks. These bottlenecks slow down the throughput of the system despite the very fast operating speed of the system's processor.
A newer type of memory known as a synchronous dynamic random access memory (SDRAM) has been developed to provide faster operation in a synchronous manner. SDRAMs are designed to operate synchronously with the system clock. That is, input and output data of the SDRAM are synchronized to an active edge of the system clock which is driving the processor accessing the SDRAM.
Some SDRAMs are capable of synchronously providing burst data at a high-speed data rate by automatically generating a column addresses for a memory array of storage cells organized into rows and columns. In addition, some SDRAMs utilize two or more banks of memory arrays which permits interleaving data between the banks to reduce access times and increase the speed of the memory.
Although SDRAMs have overcome some of the timing disadvantages of other memory devices, such as DRAMs, there is still a need for faster memory devices. Double data rate (DDR) SDRAMs are being developed to provide twice the operating speed of the conventional SDRAM. These devices allow data transfers on both the rising and falling edges of the system clock and thus, provide twice as much data as the conventional SDRAM. DDR SDRAMs are also capable of providing burst data at a high-speed data rate.
Due to the high speed data transfers, DDR SDRAMs use a bi-directional data strobe (DQS) to register the data being input or output on both edges of the system clock. According to industry standards, when data is being received by the DDR SDRAM, the DQS has a known latency which varies between 3/4 of the system clock cycle (minimum latency) to 5/4 of the clock cycle (maximum latency). When data is being received by the SDRAM, the system clock cannot be properly synchronized with the DQS because of the latency variation and thus, the system clock cannot be properly synchronized with the input data. To compensate for the latency variations, the DDR SDRAM must adjust the generation of column select addresses as each piece of input data is received so that they are synchronized with the arrival of the input data. This involves a complex writing scheme affecting the internal processing of the SDRAM and adds an unnecessary latency to the input data particularly for a burst access of several pieces of data. Accordingly, there is a desire and need for a simplified writing scheme for a DDR SDRAM which compensates for the latency variation in the DQS.